I don't know if you've commented on this, but there's a difference in the order operands are specified for scalar vs. vector assembly ops, which could cause some confusion. For example,
for scalars, there is
sub rd, rs1, rs2 does rs1-rs2 -> rd
but for vectors, there is:
vsub.vx vd, vs2, rs1, vm does vs2[i]-rs1 -> vd[i] and
vrsub.vx vd, vs2, rs1, vm does rs1-vs2[i] -> vd[i]
It's somewhat counter-intuitive until you are aware of it, but I can see why vectors are specified this way.
There was recently a similar discussion about the position of the scalar operand between the two operands of a P-extension instruction and it looks like it is going to be rs2 rather than rs! (which is the case in the V-extension). It seems other reasons (more important that this regularity) warrant this choice.
<sigh> The "clean slate" RISC-V ISA was a chance to avoid inconsistencies like this. Fortunately, this won't affect normal users, just compiler writers, those that write/read assembler/intrinsics/function libraries/emulators, and those that implement hardware.
You are right, v4 must be a GPR index here. I have corrected the example and the diagrams (the vs1 index is called rs1 when a scalar register is used). Thank you
I don't know if you've commented on this, but there's a difference in the order operands are specified for scalar vs. vector assembly ops, which could cause some confusion. For example,
for scalars, there is
sub rd, rs1, rs2 does rs1-rs2 -> rd
but for vectors, there is:
vsub.vx vd, vs2, rs1, vm does vs2[i]-rs1 -> vd[i] and
vrsub.vx vd, vs2, rs1, vm does rs1-vs2[i] -> vd[i]
It's somewhat counter-intuitive until you are aware of it, but I can see why vectors are specified this way.
There was recently a similar discussion about the position of the scalar operand between the two operands of a P-extension instruction and it looks like it is going to be rs2 rather than rs! (which is the case in the V-extension). It seems other reasons (more important that this regularity) warrant this choice.
<sigh> The "clean slate" RISC-V ISA was a chance to avoid inconsistencies like this. Fortunately, this won't affect normal users, just compiler writers, those that write/read assembler/intrinsics/function libraries/emulators, and those that implement hardware.
In the example "vadd.vx v12, v3, v4", v4 needs to be a scalar register like x4 no?
You are right, v4 must be a GPR index here. I have corrected the example and the diagrams (the vs1 index is called rs1 when a scalar register is used). Thank you