I wonder what other (HDL) tooling people use. I use SpinalHDL with the MicroSoC library developed for VexiiRiscV. If there’s any good tooling to go from HDL -> ASIC implementation (I know OpenROAD exists) , a la, closed source EDA tools I’d be very interested. I’m still kinda bummed out about the slow risc-v formal progress
What do you mean by Formal ? (Do you mean related to a formal model of RISC-V such as SAIL or about the general formalization of building an ASIC from a HDL ?)
[I don't have much experience with open source tooling to go from HDL to ASIC, I have mostly relied on the standard EDA in my professional life]
I wonder what other (HDL) tooling people use. I use SpinalHDL with the MicroSoC library developed for VexiiRiscV. If there’s any good tooling to go from HDL -> ASIC implementation (I know OpenROAD exists) , a la, closed source EDA tools I’d be very interested. I’m still kinda bummed out about the slow risc-v formal progress
What do you mean by Formal ? (Do you mean related to a formal model of RISC-V such as SAIL or about the general formalization of building an ASIC from a HDL ?)
[I don't have much experience with open source tooling to go from HDL to ASIC, I have mostly relied on the standard EDA in my professional life]
as in the Riscv-Formal project. Formal verification of a core, to prove it's upto spec. Check YosysHQ/Riscv-Formal