RISC-V Vector in a Nutshell

Introduction to RVV

Feb 03, 2023

Over the past few months we published a blog post series to introduce RISC-V Vector Extensions. Here is a list of the various posts (on the new blog):

Fprox’s Substack

RISC-V Vector extension in a nutshell (part 1)

(this article was previously published on my blog https://fprox.blogspot.com/2022/07/risc-v-vector-extension-in-nutshell.html) Introduction This article is the first of the series "RISC-V Vector Extension in a Nutshell" which presents the new vector extension for the RISC-V ISA. It covers some basic concepts of RVV (RISC-V Vector extension…

2 years ago · Fprox

Fprox’s Substack

RISC-V Vector Extension in a Nutshell (Part 2): arithmetic operations

This article is part 2 of a series on RISC-V vector extension. Part 1 introduced the series with a general overview, Part 3 surveys operations with or on masks, Part 4 describes permute instructions and Part 5.1 / Part 5.2 cover memory operations…

2 years ago · Fprox

Fprox’s Substack

RISC-V Vector Extension in a Nutshell (Part 3): mask & masked operations

This article is part 3 of a series on RISC-V vector extension, and focuses on masks. Part 1 introduces the series with a general overview, Part 2 reviews arithmetic operations, and Part 4 describes permute instructions. Part 5.1 and Part 5.2 review memory operations…

2 years ago · Fprox

Fprox’s Substack

RISC-V Vector Extension in a Nutshell (Part 4): permute operations

This article is part 4 of a series on RISC-V vector extension, and focuses on permute operations. Part 1, Introduction, is accessible here; part 2, review of arithmetic operations there; part 3, survey of operations with or on masks there. SIMD and Vector instructions sets needs to offer permutation instructions to allow the programmer to manipulate and…

2 years ago · Fprox

Fprox’s Substack

RISC-V Vector extension in a nutshell (Part 5.1): vector loads and store

This article is part 5.1 of a series on RISC-V vector extension, and focuses on vector memory operations. Part 1 introduces the series with a general overview, Part 2 reviews arithmetic operations, Part 3 surveys operations with or on masks, and Part 4…

2 years ago · Fprox

Fprox’s Substack

RISC-V Vector extension in a nutshell (Part 5.2): vector loads and store

This article is the part 5.2 of a series on RISC-V vector extension, it continues and concludes the sub-series on vector memory operations. Part 1 introduces the series with a general overview, Part 2 reviews arithmetic operations, Part 3 surveys operations with or on masks, and…

2 years ago · Fprox

Fprox’s Substack

How to read a RISC-V Vector assembly instruction

In our 5 and a half blog series, RVV in a Nutshell, we presented the basics of RISC-V Vector extension (RVV 1.0), but even after this overview some aspects of this large extension can still seem difficult to apprehend. In this sub-series, we will review in more details some of those aspects. For example, it is difficult to interpret a RVV assembly ins…

2 years ago · Fprox

Fprox’s Substack

RISC-V Vector Register Groups

The RISC-V Vector Extension (RVV) defines and exploits the concept of vector register groups. This post clarifies what a register group is, how it can be useful and the caveats associated with it. A single vector instruction can operate on operands each consisting of more than one register and can produce similarly extended results…

2 years ago · Fprox

Fprox’s Substack

RISC-V Vector Element Groups

RISC-V Vector extension has defined multiple ways to organize vector data over one or multiple vector registers. In this previous blog post we presented the concept of vector register groups defined by RVV 1.0: the capacity to group together multiple vector registers into a meta (larger) vector register which can be operated on as a single operand by mo…

2 years ago · Fprox

What are you optimizing for ? (fprox's substack)

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