RISC-V Smcntrpmf: mode filtering for Zicntr
Accurate user-mode base event counting over privilege mode flow diversion
The start of the one month public review for a new RISC-V extension: Smcntrpmf, was recently announced on August 2nd 2023 (see full announcement).
Note: This extension was developed through the fast track process, it did not originate from the standard process (e.g. lengthy public discussion in a task group) but was deemed straightforward enough and small enough that it could be submitted directly.
Smcntrpmf extends the mode-base filtering functionality of Sscofpmf to some of the base counters (Sscofpmf defined mode-base filtering for the configurable mhpmcounter counters).
Smcntrpmf specification (v1.0_rc4) can be found here (pdf). This extension introduces privilege mode filtering for some basic events counting. In particular, it improves the accuracy of user-mode event counting by allowing the system to suspend counting when the program exits user-mode and resume it when the program returns back to user-mode. It affects two base counters introduced by Zicntr: instret which counts the number of retired instructions (number of instructions executed by the hart, discarding miss-speculated instructions) and cycle (number of elapsed cycles).
Note: the mode filtering capabilities is not provided for the time base counter, making it available as a mode agnostic wall clock.
Before this extension, the number of events occurring while the program was diverted from user mode was also accumulated into the counters’ value as illustrated for instret by the figure below (the extra events counted are highlighted in bold red):
Smcntrpmf introduce two new CSRs: mcyclecfg
(address: 0x321
) and minstretcfg
(0x322
). Each of those CSRs contains 5 meaningful bits (bits 58 to 62) which can be used (when set) to independently inhibit counting in M, S/SH, U, VS, and VU modes. That means that counting events can be configured on a per-mode basis (counters accumulate events across all the non-inhibited modes) and filtering can be applied separately to any mode, not just user-mode.
Note: The new registers are 64-bit wide in both RV32 and RV64. For RV32 the default CSR address accesses the low 32-bit part of the register and high parts can be accessed through
mcyclecfgh
(0x721
) andminstrefcfgh
(0x722
).
The following diagram shows a configuration to enable only counting of events in user-mode (all other modes are inhibited). The results can be seen on the next diagram.
The bitfields’ location was aligned to the modifications of mhpmevent introduced by Sscofpmf.
The specification details how the transition from one mode to the next affect counting (e.g. how should an instruction which performs the transition actually be counted if the origin mode is not inhibited but the destination mode is).
Conclusion
Smcntrpmf allows RISC-V to provide more accurate performance measurement (when base counters are involved) by subtracting noise coming from non-user mode and, as listed in the specification, can also be used by the system to avoid leaking timing information from privilege modes into the user mode.
Public review will last until August 31rd 2023, feel free to read the detail specification (it is just over 2-page long) and share your feedback/questions on the isa-dev mailing list or directly in the specification Smcntrpmf github repository issue section.
Reference(s):
Specification source repository: https://github.com/riscv/riscv-smcntrpmf (also a good place to open Issue and ask questions during the public review process)
RISC-V technical session on performance monitoring status (August 3rd 2023): https://sites.google.com/riscv.org/riscv-technical-sessions/home#h.ogmw9l7jypav